1. Field of the Invention
The invention relates to a process of producing integrated MOS circuits and somewhat more particularly to producing integrated MOS circuits with and without MNOS memory transistors constructed in silicon-gate technology and provided with overlapping contacts, using a silicon nitride mask.
2. Prior Art
One of the most important goals in production of highly integrated semiconductor circuits is to accommodate as many circuit components (i.e., transistors) or functional units as possible per unit area, on a basis of a minimum, controllable structure size. The inactive regions of a circuit, i.e., those regions which do not directly contribute to the circuit function, are particularly troublesome in achieving such goals. Such inactive regions include the non-utilizable zones at the periphery of contact holes. These inactive zones result from requisite safety spacings.
Currently, polysilicon technology is mainly used for production of MOS components. In this technology, the gate electrodes of field effect transistors and conductor leads or interconnections which function to connect such electrodes are formed from polysilicon. The main advantage of this technology, in contrast to a technology wherein such electrodes and conductor leads are composed of aluminum, is that the disturbing gate-source and gate-drain overlap capacitances can be kept very small and the polysilicon forms an additional level of interconnection.
In n-channel and p-channel silicon and double silicon-gate technology, it is necessary to produce contact holes in SiO.sub.2 layers, both on n.sup.+ - and p.sup.+ -doped monocrystalline silicon zones as well as n.sup.+ - and p.sup.+ -doped polycrystalline zones. It is also necessary to insure that part of the area of a contact hole does not project beyond the zone which is to be contacted, since otherwise a danger exists that the metallic conductor lead which is later applied over such contact hole can produce a short-circuit to an adjacent p- or n-doped zone of a monocrystalline silicon substrate. In the event that a contact hole projects beyond a polysilicon structure, there is also a danger that underetching of SiO.sub.2, under the polysilicon structure, can produce an overhang of the polysilicon structure, which can cause an interruption of the overlying conductor lead.
In order to prevent contact holes from projecting beyond these zones which are to be contacted, it is necessary to provide safety spacings between the edges of the contact holes and the edges of the adjacent doped silicon zones. Such safety spacings are necessary because the distance between two structure edges in two different levels cannot be attained with arbitrary accuracy but only within a specific tolerance range, which with present prior art technology, is about .+-.2 .mu.m.
The prior art is aware of various means of minimizing or rendering unnecessary the earlier described safety spacings at peripheries of contact holes.
German Offenlegungesschrift (hereinafter DE-OS) No. 27 23 374 describes a process wherein the oxidation-inhibiting effect and the etch-stop effect of nitride layers are exploited to provide contact holes having base areas which project beyond the polysilicon zones which are to be contacted. However, this process requires an additional contact hole mask; safety spacings must still be provided at the peripheries of contact holes between monocrystalline n.sup.+ - and p.sup.+ - doped zones and the metallic interconnections or leads; and the slopes of the contact holes are extremely steep or even overhanging.
V. L. Rideout et al, "A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-to-Polysilicon Contact", International Electron Devices Meeting, Technical Digest, Washington, U.S.A., page 258 (December 1977) suggests that a those points at which contact holes are to be formed, the polysilicon layer can be covered by a double layer of silicon dioxide. Those portions of the polysilicon layer which are not covered, are etched away. This procedure also involves the disadvantages of the process described in DE-OS No. 27 23 374, with the difference that the slopes of the resultant polysilicon structure (and not of the contact holes) are overhanging.
W. G. Oldham et al, "Improved Integrated Circuit Contact Geometry Using Local Oxidation", Electrochemical Society Spring Meeting, Seattle, U.S.A., page 960 (May 1978) suggests that an oxidation-inhibiting silicon nitride layer be applied after etching of the polysilicon layer. This nitride layer is then etched in such a manner that it only remains at the points where contact holes are to be formed. A disadvantage of this process is that the slopes of the resultant polysilicon structures can overhang and in instances where contact holes are arranged partially or completely on gate zones, the earlier described safety spacings from the polysilicon edges are still required.
A process which minimizes or renders superfluous the safety spacings at peripheries of contact holes between monocrystalline n.sup.+ -doped zones and metallic interconnections is disclosed in DE-OS No. 25 09 315. In this process, after etching of the contact holes, a dopant (phosphorus or arsenic) is introduced into the contact hole walls. With this measure, in the event of projecting contact holes, a short-circuit between monocrystalline n.sup.+ -zones and adjacent p-doped zones is prevented. However, this process still requires safety spacings at peripheries of contact holes adjacent to polysilicon structures.